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Fetch Decode and Execute

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Introduction

Ricki Lambert Computer Systems Fetch, Decode and Execute Introduction In this task I will be describing in detail the function of the fetch-decode-execute cycle and its relationship to the workings of a microprocessor, whilst making detailed reference to the role played by hardware and software in this relationship. The fetch, decode and execute cycle is formally known as the machine cycle. This cycle undergoes numerous steps incorporating the hardware from inside the processor mainly and the software stored in the disk space. To make sure the processor knows where to find a particular programme stored in memory it is assigned a number which is stored in the control logic area of the processor. It is in this area of the processor that instructions are decoded and obeyed. When fetching from the memory the processor uses a two logical systems of retrieval and they are; Fixed address reset system - This system normally loads from the bottom of the memory Vectored system load - This normally starts from the start address from a set place in memory and this can be either at the bottom or top of memory To counteract this, a jump function is used allowing the processor to fetch any instruction from any place in memory. ...read more.

Middle

In the diagram below we can see an example of the code working to a real situation, the situation being the programme code written in the microsim package. Fetch Decode and Execute Cycle Including Example To fetch the instructions from memory data has to travel along a series of communications links, these are called busses. There are a few differing types of busses that can be used. Whenever the CPU needs to read or write a byte of data to or from the memory it will specify the address on the address bus. This data is then placed on another communicational channel called the data bus. The data bus is what is known as unidirectional, and this means that the CPU can specify addresses but the memory cannot. This is a stark contrast to the data bus where both CPU and memory can place information on it, this is called bidirectional. This takes us to the control bus where similarities lie with the control unit. Where the control unit is the power behind the processor, the control bus is the power behind the bus system. The control bus will dictate whether the information is to be read or write, to be sent from memory to processor and visa versa and also whether all information on other busses is ready. ...read more.

Conclusion

Now that the two values have been extracted from the memory this means the fetch part of the cycle has been completed. The data is now placed in to the instruction register so the control unit can begin the process of decoding the values in to some form of useable data. This data is what will present us with an answer. This is done by the arithmetic logic unit. When in the ALU, the decoded information is able to be processed. Processing this data is dependant on the opcode that is presented when in the decoding stage. This will determine how the data is processed, whether it is add, subtract and so on. When processed the data is either stored in the main memory or projected to an output device. But how does the CPU no where to send it? Based on the conditional feedback from the ALU the CPU is able to determine where the information is to be sent to. It is this command that determines what bus route to send the required / processed data through. Things get a lot trickier when the jump command is issued. However if using my example diagram, instead of adding the programme counter by two it will dictate where the next instruction is to go by altering the programme counter to suit. This can be done in various ways. ...read more.

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