Digital System Design

Signal names: A comma- separated list of one or more user selected identifiers to name the external interface signals

Mode: This specifies the signal direction

   In: The signal is an input to the entity

   Out: The signal is an output of the entity. The values of such a signal cannot be read inside the entity’s architecture only by other entities that use it.

Buffer: The signal is an output of the entity and its value can also be read inside the entity that uses it.

Inout: The signal can be used as an input or an output of the entity. This mode is typically used for three state input/output pins on the PLDs.

Signal-Type: a built in or user defined signal type. We’ll have a lot to say about types in the next subsection.

Note that there is no semicolon after the final stage-type; swapping the closing parenthesis with the semicolon after it is a common syntax error for beginning VHDL programmers.

An entity’s ports and their modes and types are all that is seen by other modules that use the entity. The internal operation of the entity is specified in its architecture definition. The entity name in this definition must be the same as the one given in the entity declaration. The architecture name is a user selected identifier usually related to the entity name. The declarations can appear in any order. The signal declaration gives the same information about a signal as in a port declaration except that no mode is specified example signal signal-names : signal-type;

Zero or more signals can be defined in an architecture and they can approximately correspond to names wires in the logic diagram. They can be read or written within the architecture definition and like other local objects can be referenced only within encompassing architecture definition.

A VHDL library is a place where the VHDL complier stores information about a particular design project including intermediate files used in analysis, simulation and synthesis of the design. The complier automatically creates and uses a library for a given VHDL design.

Programmable logic arrays historically were the first programmable devices. The PLA’s contains a two-level structure of AND and OR gates with user programmable connections. By the use of the structure, a program designer can accept any logic function up to a certain level depending on how difficult it is. This can be determined by the use of logic synthesis and minimisation. The PLA structure was improved whereby the costs were reduced with the introduction of programmable array logic (PAL) devices.

Read Only Memory

Read only memory is often referred as a class in the storage media used in computers and other electronic devices. This cannot be easily written into so it is mainly used in the distribution of firmware. Firmware is software that is very closely related to hardware and not likely to need frequent upgrading. Modern  ROMs typically take the shape of  packages,which is (computer chips), not immediately distinguishable from other chips like  but for the text printed on the chips. "ROM" in its strictest sense can only be read from, but all ROMs allow data to be written into them at least once, either during initial manufacturing or during a step called "programming". Some ROMs can be erased and re-programmeda multiple number of times, although they are still referred to as "read only" because the reprogramming process involves relatively infrequent, complete erasure and reprogramming, not the frequent, bit- or word at a time updating that is possible with  (RAM).

Full Adder

A full adder is a combinational circuit that forms the airthmetric sum of three bits. It consists of three inputs and two outputs. Two of the input varaibles, denoted by A and B, represent the two significant bits to be added. The third input,Cin,represents the carry from the previous lower significant position.

The truth table

D flip flop

The state of a latch or flip flip is switched by a change in control input. This change is called a trigger and it causes the flip flop to trigger. The D latch with pulses in its control input is essentially a flip flop that is triggered every time the pulse goes to the logic 1 level. As the pulse input remains in the same level, any change in the data input will change the output and the state of the latch.

The circuit samples the D input and changes its output only at the negative-edge of the controlling clock. When the clock is 0, the output of the inverter is 1. The slave latch is enabled and its output is equal to the master output. The master latch is disables because CLK=0. When the input pulse changes to the logic 1 level, the data from the external D input is transferred to the master. The slave is then disabled as long as the clock remains in the 1 level because its input is equal to 0. If there is any change in the input changes the master output, but cannot affect the slave output. When the pulse goes back to a value of zero, then the master will be disabled and isolated from the D input but a the same time the slave is enabled and the value of the master output is transferred to the output of the flip flop at output.

The truth table:

The XCRP board provides an ideal platform for new engineers requiring experience with basic digital design techniques, as well as those needing exposure to Xilinx CAD tools and CPLD devices. XCRP board features include:

∙  A socketed Xilinx XCR3064 CPLD.

∙  Non-volatility – designs remain in the CPLD after power is removed.

∙  On board voltage regulator for use with a wall-plug transformer, or the board can run more than 60hrs on 2 AA cells (typical).

∙  Expandability –an integral solderless breadboard allows expansion circuits to be constructed right on the XCRP board.

∙  An user-adjustable oscillator circuit (Approximately 0.5Hz to 4 KHz)

∙  JTAG programming using a standard parallel cable (included)

∙  Two high-bright seven segment displays.

∙  Four debounced buttons;

∙  Eight slide switches;

∙  Eight LEDs in three colors (red, green, and yellow).

∙  40-pin expansion connector.

CPLD (complex programmable logic device)

The design of a digital system using PLD usually requires the connection of many devices to produce the full specification. With regards to this type of application, it will be cheaper to use a complex programmable logic device (CPLD). A CPLD is a collection of individual PLDs on a single integrated circuit. A programmable interconnection structure allows the PLDs to be connected to each other in the same way that it can be done with the individual PLDs.

Discussions (Results)

The diagram of the logic circuit for the entity below        :

Explaining the program shown below

1. This shows that a, b and c are the inputs of the full adder
2. The s, c_out are the outputs or results of the full adder whereby s represents the sum and the c_out the carrier.
3. This shows that s (output) can be generated from a xor b xor c_in (inputs) which represents exclusive –OR(XOR)
4. This shows that c_out(output) can be generated from (a and b) or (a and c_in) or (b and c_in) which is the same as (a * b) + (a*c_in) + (b*c_in) to give the output carry

Explaining the lines marked in the program below

 This describes the ports and directions for the full adder’s test bench.

This shows the input and output ports of the full adder

These are signals that are used to control the values during the test. They have different signal and ports so therefore have different names.

This suspends the process indefinitely.

The output waveform

The D flip flops

This shows a condition such that when the clock=1 then D will be connected to Q.

1. This shows that the signal for the clock should remain 1
2.  This shows that the value of the clock should be negated to 0 after 50ns.

The waveform for D flip flop

Can you explain the choice of these test signals with respect to the expected behaviour of a positive edge triggered D flip-flop?

The choice of the test signal is when the pulses of the clock goes through two signal transitions from 1 to zero and return with 0 to 1..

This indicates the library were all the commands are stored.

the statement of the portmap links the component parts to the circuit. It makes al list of the architecture signals that is needed such as A.B.Ci,S1,Cn

This is end all the processes.

this shows the connection between the full adder and the d flip flop

This means that after 80ns the value of a will be 1.

This creates a loop in which it increases by one. So therefore, it would pass through N three times.

This means that when the bit is low then it will have to perform a certain actiom

This means that when the bit is other than low then it will have to form a different set of actions.

The carry out is connected to the second signal.

yes they are correct.

This proves that the program board has a READ ACCESS MEMORY (RAM) which means that the data will remain on the board until it is overwritten.

This proves that the program board also has a READ ONLY MEMORY (RAM) which means that the program will still remain even if the power is disconnected.

• the debounce button works by a trigger. Once it had been triggered, it changes the state of count thereby sending a message to the circuit. When the BN1 button was pressed, the left hand side missed a count while the right continued counting. When the BN2 button was pressed, the right side missed a count while the left side continued counting. When the BN3 button was pressed, the left hand side and the right both missed a count. When the BN4 button was pressed, there was an increase in counts which resulted to the lights to move faster.
• The potentiometer is used to control the frequency, when it’s turned it gives values like 11, 22,33,44,55,66,77,88 and 99. A bounce happens when there is a short delay from the switch settling into its final state. The process of eliminating this effect is known as debouncing. This can be done by removing the transitions in the signal to make sure that only one value is recorded when the button is pushed. The debounce can be introduced to my design by making use of wait.

The three bit counter

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity three_bit_add_counter is

port

        ( N : in std_logic_vector (2 downto 0);

         CLK, RESET, CIN: in std_logic;

         OUT1 : out std_logic_vector (2 downto 0);

         COUT : out std_logic);                

end three_bit_add_counter;

architecture Behavioral of three_bit_add_counter is

         component three_bit_add

         port(N1, N2 : in std_logic_vector (2 downto 0);

                        CLK, RESET, CIN : in std_logic;

                   SUM : out std_logic_vector (2 downto 0);

                   COUT : out std_logic);

end component;

signal s1 : std_logic_vector (2 downto 0);

begin

a1 : three_bit_add port map (s1,N,CLK,RESET,CIN,s1,COUT);

OUT1 <= s1;

                  

end Behavioral;

The Three bit counter test bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

USE ieee.numeric_std.ALL;

ENTITY three_bit_add_tb_vhd IS

END three_bit_add_tb_vhd;

ARCHITECTURE only_arch OF three_bit_add_tb_vhd IS

    component three_bit_add

        port

        (

            n1    : in std_logic_vector (2 downto 0);

            n2    : in std_logic_vector (2 downto 0);

            cin   : in std_logic;

            clk   : in std_logic;

            reset : in std_logic;

            sum   : out std_logic_vector (2 downto 0);

            cout  : out std_logic

        );

    end component;

    SIGNAL sig_n1    : std_logic_vector (2 downto 0) := "000";

    SIGNAL sig_n2    : std_logic_vector (2 downto 0) := "000";

    SIGNAL sig_cin   : std_logic := '0';

    SIGNAL sig_clk   : std_logic := '1';

    SIGNAL sig_reset : std_logic := '0';

    SIGNAL sig_sum   : std_logic_vector (2 downto 0);

    SIGNAL sig_cout  : std_logic;

BEGIN

    uut: three_bit_add

        port map

        (

            n1    => sig_n1,

            n2    => sig_n2,

            cin   => sig_cin,

            clk   => sig_clk,

            reset => sig_reset,

            sum   => sig_sum,

            cout  => sig_cout

        );

    sig_clk <= not sig_clk after 50 ns;

    tb : PROCESS

    BEGIN

        wait for 90 ns;

        sig_reset <= '1';

        wait for 20 ns;

        sig_n1 <= "001";

        wait for 10 ns;

        sig_reset <= '0';

        wait for 70 ns;

        sig_n2 <= "001";

        wait for 100 ns;

        --TJP  sig_n1 <= "001";

        sig_n2 <= "111";

        --TJP  wait for 30 ns;

        sig_n1 <= "010";

        wait for 30 ns;  --TJP

        wait for 70 ns;

        sig_n1 <= "011";

        sig_n2 <= "011";

        wait for 100 ns;

        sig_cin <= '1';

        wait for 100 ns;

        sig_cin <= '0';

        wait;

    END PROCESS;

END only_arch;

The Output waveform

Design implementation

1. I had to take notice of the array size because it resulted in some errors
2. Had to ensure that the timing was reliable

Six bit counter adder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity six_bit_add is

 PORT(     n1    : in std_logic_vector (5 downto 0);

        n2    : in std_logic_vector (5 downto 0);

        cin   : in std_logic;

        clk   : in std_logic;

        reset : in std_logic;

        sum   : out std_logic_vector (5 downto 0);

        cout  : out std_logic);

end six_bit_add;

architecture Behavioral of six_bit_add is

component f_fadff

                        port(  f_a     : in  std_logic;

            f_b     : in  std_logic;

            f_ci    : in  std_logic;

            f_clk   : in  std_logic;

            f_reset : in  std_logic;

            f_cn    : out std_logic;

            f_s     : out std_logic);

        end component;

signal s1 : std_logic_vector (5 downto 0);

begin

inst : for i in 0 to 5 generate

        LowBit : if i = 0 generate

        FCT : f_fadff port map (f_a     => n1(i),

                    f_b     => n2(i),

                    f_ci    => cin,

                    f_clk   => clk,

                    f_reset => reset,

                    f_cn    => s1(i),

                    f_s     => sum(i)

                    );

                       

                        

        end generate;

        OtherBit : if i /= 0 generate

        FCT : f_fadff port map (

                   f_a     => n1(i),

                    f_b     => n2(i),

                    f_ci    => s1(i-1),

                    f_clk   => clk,

                    f_reset => reset,

                    f_cn    => s1(i),

                    f_s     => sum(i));

                         

                                                 

        end generate;

end generate;

cout <= s1(2);

end Behavioral;

Six bit adder counter

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity six_bit_add_counter is

 port

        ( N : in std_logic_vector (5 downto 0);

         

         CLK, RESET, CIN: in std_logic;

         OUT1 : out std_logic_vector (5 downto 0);

         

         COUT : out std_logic);                

end six_bit_add_counter;

architecture Behavioral of six_bit_add_counter is

  component six_bit_add

         port(N1, N2 : in std_logic_vector (5 downto 0);

                         

                        CLK, RESET, CIN : in std_logic;

                   SUM : out std_logic_vector (5 downto 0);

                        

                   COUT : out std_logic);

 end component;

signal s1 : std_logic_vector (5 downto 0);

begin

 b1 : six_bit_add port map (s1,N,CLK,RESET,CIN,s1,COUT);

OUT1 <= s1;

end Behavioral;

Six bit adder counter testbench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY six_bit_add_counter_tb_vhd IS

END six_bit_add_counter_tb_vhd;

ARCHITECTURE behavior OF six_bit_add_counter_tb_vhd IS

        -- Component Declaration for the Unit Under Test (UUT)

        COMPONENT six_bit_add_counter

        PORT(

                N : IN std_logic_vector(6 downto 0);

                CLK : IN std_logic;

                RESET : IN std_logic;

                CIN : IN std_logic;          

                OUT1 : OUT std_logic_vector(6 downto 0);

                COUT : OUT std_logic

                );

        END COMPONENT;

        --Inputs

        SIGNAL CLK :  std_logic := '0';

        SIGNAL RESET :  std_logic := '0';

        SIGNAL CIN :  std_logic := '0';

        SIGNAL N :  std_logic_vector(6 downto 0) := (others=>'0');

        --Outputs

        SIGNAL OUT1 :  std_logic_vector(6 downto 0);

        SIGNAL COUT :  std_logic;

BEGIN

        -- Instantiate the Unit Under Test (UUT)

        uut: six_bit_add_counter PORT MAP(

                N => N,

                CLK => CLK,

                RESET => RESET,

                CIN => CIN,

                OUT1 => OUT1,

                COUT => COUT

        );

        tb : PROCESS

        BEGIN

        wait for 90 ns;

                RESET<='1';

                wait for 20 ns;

                RESET <= '0';

                N <= "001000";

                wait for 30 ns;

                N <= "010000";

                wait for 50 ns;

                N <= "011000";

                wait for 70 ns;

                N <= "100000";

                wait for 90 ns;

                N <= "101000";

                wait for 100 ns;

                CIN <= '1';

                wait for 100 ns;

                CIN <= '0';

                                

                wait;

        END PROCESS;

END;

Conclusion

This experiments above has made me reach most of my learning objective above but I found the binary adder and subtractor difficult to do because it resulted in some any errors.

References:

1. M.Morris Mano (2002),Digital circuit design third edition, Prentice Hall
2. John F Wakerly (2006), Digital Design Principles and Practices, Prentice Hall
3. Jerry D. Daniel (1996), Digital Design from zero to one, John Wiley and Sons Inc.