Measurement of Processors Performance report. In the experiment, a testing code was developed in C Programming Language. The design involved filling up each memory hierarchy level with data, then by noting down the time taken to access each level, the ban

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Measurement of Processors Performance

Commissioned by THE UNIVERSITY OF AUCKLAND

Written by

Electrical and Electronic Department (EED)

COMPSYS 304 - Computer Architecture

10. 05

Table of Contents

Introduction 3

1. Experiment Overview 4

1.1 Theoretical Background 4

1.2 Testing Platform 5

2. Theoretical Prediction 6

2.1 Hypothesis 6

2.2 Estimation Calculation 6

3. Design Methodology 7

3.1 Experimental Achievement 7

3.2 Experimental Implementation 7

3.3 Experimental Errors 7

4. Result 8

5. Discussion 10

6. Conclusion and Recommendation 11

7. List of References 12

Table of Figures

Figure 1 Memory Hierarchy 3

Figure 2 Design Strategy 4

Figure 3 Graph of Data Transfer Rate versus Array Size for Sequential Access for Core i7 975 EE 8

Figure 4 Graph of Data Transfer Rate versus Array Size for Sequential Access for Core i5 750 8

Figure 5 Average Data Transfer Rate Comparison between Core i7 EE and Core i5 750 9

Figure 6 Comparison of Bandwidth between Core i5 750 and Core i7 975 EE 10

Introduction