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Measurement of Processors Performance report. In the experiment, a testing code was developed in C Programming Language. The design involved filling up each memory hierarchy level with data, then by noting down the time taken to access each level, the ban

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Measurement of Processors Performance        image07.jpg

Measurement of Processors Performance        


Written by

Electrical and Electronic Department  (EED)

        COMPSYS 304 – Computer Architecture    

10. 05

Table of Contents


1.Experiment Overview

1.1Theoretical Background

1.2Testing Platform

2.Theoretical Prediction


2.2Estimation Calculation

3.Design Methodology

3.1Experimental Achievement

3.2Experimental Implementation

3.3Experimental Errors



6.Conclusion and Recommendation

7.List of References

Table of Figures

Figure 1 Memory Hierarchy

Figure 2 Design Strategy

Figure 3 Graph of Data Transfer Rate versus Array Size for Sequential Access for Core i7 975 EE

Figure 4 Graph of Data Transfer Rate versus Array Size for Sequential Access for Core i5 750

Figure 5 Average Data Transfer Rate Comparison between Core i7 EE and Core i5 750

Figure 6 Comparison of Bandwidth between Core i5 750 and Core i7 975 EE


In modern computers, the memory is always divided into multiple levels, which are structured into a memory hierarchy (Figure 1). In the memory hierarchy, each level is distinguished by the response time with the top-most level being the fastest. In most computers, this level is the processor registers which are often accessed in one CPU clock cycle. The next level is the Level 1 (L1) Cache, which is temporally and physically closest to the main processor. The third level is usually the Level 2 (L2) Cache and the forth level is the main memory [1].

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* Values are estimated based on research, no official documentation

  • Motherboard:               Asustek RAMPAGE II EXTREME Intel X58
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  1. Theoretical Prediction

  1. Hypothesis

For the sequential access to the memory, we expect to observe four distinct levels on the graph, corresponding to accessing the L1 cache, the L2 cache, the L3 cache and the main memory. The reason for this expectation is that the accessing time will increase significantly when there is a transition between different memory hierarchies. [6] For the random access to the memory, a graph of an exponentially decrease in the data transfer rate should be seen, as the current level of memory hierarchy is saturating. Then it should level off at a particular value since the memory size of the current level is exceeded.

  1. Estimation Calculation

  • Intel Core i7 975 Extreme Edition:

Bandwidth for L1 Cache = processor speed x bus width

                                                                = 3300 MHz x 32 bytes = 106,000* MB/s ± 10MB

                        Bandwidth for L2 Cache = processor speed x bus width

                                                                = 3300 MHz x 16 bytes = 52,800* MB/s ± 10MB

             Bandwidth for Main Memory = memory speed x bus width x 2

                                                  = 133 MHz x 8 bytes x 2 = 2,130* MB/s

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Alternatively this could have been done on Linux using gcc O4 which would run with the maximum optimization [9].Latency of the processor should be found by using 3rd party software and should be considered for the testing stage [10].Enough repetitions of the memory access should be performed to obtain more reliable results.
  1. List of References

  1. Comer, D. E. (2005) Essentials of Computer Architecture. Pearson/Prentice Hall, USA (New Jersey)
  2. Wikipedia (2009) from http://en.wikipedia.org/wiki/Memory_hierarchy

Retrieved 29 September 2009.

  1. Corei7ee (2009) from www.intel.com/design/corei7ee/documentation.htm

Retrieved 29 September 2009.

  1. Corei750 (2009) fromwww.intel.com/design/corei5_750/documentation.htm

   Retrieved 29 September 2009

  1. A.Swan(2008), MEMORY HIERARCHDESIGN ,from

http://www.cs.iastate.edu/~prabhu/Tutorial/CACHE/mem_title.htmlRetrieved 29 September 2009.

  1. V.Guistin(2004), Fast Data Dependence Analysis in a Multimedia Vectorizing Compiler,
    Proceedings of the 12th Euromicro Symposium on Parallel and Distributed Computing 2004,
    PDP 2004, February, 11–13, La Coruna, Spain, pp. 176–183. 2004.
  1. Assoc. Prof. John Morris and Dr. Morteza Biglari-Abhari(2009) “Computer architecture”, Lecture/class university of Auckland, New Zealand. Unpublished.
  1. David A. Patterson, John L. Hennessy(2009) Computer organization and design : the hardware/software interface ,4th ed.Amsterdam ; Boston : Elsevier Morgan Kaufmann, c2009
  1. Nils J. Nilsson(2007), computer architecture - A New Synthesis, Morgan Kaufmann Publishers, 2000.
  1. H.joshon(2006) Software Architecture and Design, from

Retrieved 29 September 2009


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