The standard PC parallel interface and the sequence of events of the transmission of data:

       Data

 Address

  Control                                                                                                                                                              

The data bus is the most important bus as it is used to transfer information (data) from the processor to memory and vice versa. This data may be machine code instructions, ASCII codes, graphics data, etc. Since the required data may need to be read from or written to any memory location, the processor must have a way of selecting which memory location is required. This means that each memory location must have a unique number, which is called an address. The processor defines this address by placing the appropriate binary pattern (binary) number on the address bus and this selects a unique memory location.

This would be the sequence of events during the transmission of data to a printer.

• Read:     A signal from the processor that initiates a memory read operation once the address bus has been set up with the address.
• Write:    A signal from the processor that initiates a memory write operation once the address bus and the data bus have been set up.
• Clock:    The signal into the computer consists of a regular sequence of pulses. All key events are timed to take place at particular points within the on/off cycle of each pulse.
• Reset:    This is a signal into the processor, which when activated, clears all internal processor registers and starts fetching instructions from a predefined place.
• Interrupt:    This is a signal into the processor which, when activated, causes the current state of processing to be saved in a temporary area (called the stack). The processor then deals with the device that made the interrupt, returning to the previous operation when the interrupt is complete. Some machine code instructions can tell the processor to ignore or “mask” the interrupt system.
• NMI:    This signal into the processor operates in the same way as the “interrupt” signal except that the NMI (non-maskable interrupt) cannot be “masked”.