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Logic gates

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Task 1 For each of the gates listed below, explain their operation showing appropriate gate symbols, truth tables and logic equations for the outputs in terms of the input variables. a) Two input OR gate Logic gates process signals which represent true or false. Normally the positive supply voltage +Vs represent true and 0V represents false. Other terms which are used for the true and false states are shown in the table on the right. It is best to be familiar with them all. The output Q is true if input A OR input B is true (or both of them are true): Q = A OR B An OR gate can have two or more inputs, its output is true if at least one input is true. Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 1 Traditional symbol IEC symbol Truth Table b) Two input AND gate The AND gate is a digital logic gate that implements logical conjunction - it behaves according to the truth table to the right. ...read more.


the NOR gate Z = A.B.C + A.B.C + A.B.C + A.B.C A B C Z 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 Task 5 For this task I was asked to produce a minimized circuit. I did this by using the karnaugh map below. BC A 00 01 11 10 0 1 1 1 1 1 The minimized equation for this circuit is: A.B + A.C + B.C I built this circuit, using the same equipment as previous, such as the logic probe etc. this circuit does the function as the original circuit, but only this time there are less components used. This has many benefits, as it makes the entire circuit cheaper to build, and the person building the circuit is less likely to make a mistake in the construction of it. Task 6 Compare and contrast, with reference to five characteristics the differences between the 2 types of logic family listed below. ...read more.


On the CMOS, the delay ranges from 95-40ns. The propagation delay time, is the time it takes to send the signal from the sender to the receiver. TTL would be the best suited for changing signal outputs quickly. The TTL supply current ranges from 11-33mA. CMOS ranges from 1-30A. the CMOS chip requires less amps to operate, so for it would be better suited for low power circuits. The TTL needs 4.75-5.25V, whilst CMOS chip requires between 3-15V. this means the CMOS chip would be the best for altering voltage. This makes CMOS the most useful. TTL can operate at a temperature range of 0-70C. The CMOS chip again beats this, because it has a superior temperature operating range of -40-+85C. CMOS wins this because it is best suited to large temperature changes. The high level output voltage on the TTL chip is 2.4v, whilst the CMOS has an output voltage, of 2 thirds that of the input voltage. E.g. if the input voltage is 5V, the output is 3.333V. In conclusion I feel that the CMOS chip is the superior chip for today's demands. The only area that CMOS is outperformed by TTL is the Propagation Delay Time. This means CMOS is a great chip. ?? ?? ?? ?? Gavin O'Hara ...read more.

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